A programmable logic device, such as a complex programmable logic device (CPLD) or a field programmable gate array (FPGA) is designed to be user-programmable so that users can implement logic designs of their choices. In a typical FPGA, an array of configurable logic blocks (CLBs) are coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. These CLBs, IOBs, and programmable routing resources are customized by loading a configuration bitstream into configuration memory cells of the FPGA. As circuit designs implemented in an FPGA are becoming more complex, the number of CLBs, IOBs, and/or other resources (e.g., multipliers and block RAMs) has increased, as well as the routing resources to make the connections between the various blocks. As a result, the size of FPGA die and the resources fabricated on the die has grown. Because the number of defects is proportional to the area of a die, the probability of having a defect in a die has also increased.
The circuits implemented by different customers using FPGAs are generally unique. In some cases, customer designs may require more than one FPGA. Further, a circuit design may undergo modifications during product development phase. Thus, multiple versions of a circuit may be implemented on an FPGA. If an FPGA contains a single defect (e.g., one of its configuration memory cells is defective), it may render an end product unusable because the design may need to use that defective resource. Accordingly, the problem of low yield has significant economic impact on FPGA manufacturers.
While a gross defect causes failure of an entire FPGA, a localized defect causes failure of small circuitry in the FPGA. In order to avoid problems with customers, an FPGA manufacturer needs to discard an FPGA even if it contains only one defect. It has been found that a majority of large FPGA dies are discarded because of localized defects. Methods have been found to use some of these defective dies, thereby reducing the cost of product of the FPGA manufacturer. In particular, it may be determined that a defect in a given FPGA die will not affect the customer's design, making that given defective die suitable for the customer. For example, a user may program a predetermined circuit design. If the design works, the die would be acceptable to the customer. As a result, customers can take advantage of lower priced FPGAs for specific design patterns. However, some applications of programmable logic devices require that configurable logic blocks of the programmable logic device be reprogrammed. Defective die are typically not suitable for such applications because a defective die which may have been suitable for a predetermined design may not be suitable for a revised design.
Accordingly, there is a need for an improved circuit for and method of implementing defective programmable logic devices.